Process for receiving a signal coded and modulated according to an ETS-HIPERLAN standard

ABSTRACT

A method and apparatus for receiving a signal by the ETS/HIPERLAN standard. In the method decoding is done by the BCH standard. Differential pre-coding is done and integration for cancelling transmitter side differential pre-coding is done only after BCH encoding. The apparatus contains a non-coherent demodulation a BCH decoder and an integrator.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for simplifyinga signal coded and modulated by the ETS (European TelecommunicationStandard)--HIPERLAN (High Performance Radio Local Area Network).

2. Description of the Prior Art

The so-called European Telecommunications Standard (ETS) defines thetechnical characteristics of a wireless local high performance network(High Performance Radio Local Area Network=HIPERLAN). HIPERLAN is ashort-range communications subsystem with a high data rate (compare ETSI1995, ETS 300 652, UDC: 621 396).

The ETS-HIPERLAN standard is intended for USC in the 5.15 to 5.30 GHzfrequency band.

The HIPERLAN standard exactly defines the mapping of data onto thetransmitted signal which is effected by coding and modulation. Areceiver for a signal structured in this way can accomplish inversemapping by sequentially cancelling the operations undertaken in thetransmitter for generating the transmitted signal. For a receiver whichis based on coherent demodulation this is not a problem for the mostpart in a transmitted signal formed according to the HIPERLAN standard.

Noncoherent demodulators are somewhat less complex than coherentdemodulators and would be advantageous for HIPERLAN. But it happens thatthe step-by-step cancellation of the encoder and modulation stages innoncoherent reception leads to behaviours causing fatal error.

DESCRIPTION OF THE INVENTION

The object of the invention is to devise a process for receiving asignal which is coded and modulated according to an ETS-HIPERLANstandard, which makes do with a receiver structure as simple aspossible, and which achieves a packet error rate as close as possible tothat of a coherent receiver.

The solution according to the invention is defined by the method andapparatus disclosed. The invention is based on the finding that encoderand modulation steps during reception should not be inverted incorresponding steps of the method. Differential precoding should only becancelled after de-interleaving and BCH (Bose Chaudhuri-Hocquenghem)decoding. In signal transmission the sequence of steps relevant to theinvention is not "BCH coding--differential precoding--inversion ofdifferential preceding--inversion of BCH coding", but "BCHencoding--differential preceding--inversion of BCH coding--inversion ofdifferential preceding". Of course, other different processing steps canbe inserted in front of, between, and after the indicated stepsdescribed relevant to the invention.

The sequence of steps according to the invention entails the fact thatthe first code word of a data packet on the receiver side is no longernecessarily a BCH code word. There are now different possibilities fortaking this circumstance into account. According to a first preferredembodiment the first code word is excluded by error correction. (Sincethe BCH code used is systematic, the first 26 bits which containinformation are output and the remaining 5 bits are simply deleted. Thisis thus possible for any systematic code). The first code word istherefore passed essentially unprocessed by the BCH decoder.

Another version consists in that the first code word is processed with asoft decision decoding process which ignores only the first bit of thecode word. With soft decision coding therefore also the first word canbe protected to a certain degree against errors. However errorprotection is less than in the other 15 BCH code words, since theminimum Hamming distance is only 2 instead of 3. The computer cost issomewhat greater in this decoding. One example of a soft decision codingprocess is so-called erasure decoding. In erasure decoding the bit whichwas subject to the greatest error probability or decision-makinguncertainty in detection is erased and replaced by the expected one.

In integration (for canceling the differential preceding) the last bitof the immediately preceding synchronization sequence is used forinitialization.

A circuit for executing the process thus has a non-coherent demodulator,a circuit which is directly connected in terms of the signal stream forde-interleaving and BCH decoding, and only adjacent thereto anintegrator. The digital part of the noncoherent demodulator,de-interleaving, BCH decoding and integration can be combined in asingle signal processor. Hardware and software implementation of theprocess according to the invention does not pose any specialdifficulties to one skilled in the art.

Other details and combinations of features follow from the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings used to explain the embodiment show the following:

FIG. 1 illustrates the structure of a data packet according to theHIPERLAN standard;

FIG. 2 illustrates a block diagram with the important coding andmodulation steps according to the HIPERLAN standard;

FIG. 3 illustrates a block diagram of a receiver according to theinvention.

FIG. 4 illustrates a brown coherent receiver in flow chart form.

FIG. 5 illustrates a preferred method in flow chart form.

Essentially the same parts are labelled with the same reference numbersin the different Figures.

EMBODIMENTS OF THE INVENTION

HIPERLAN uses burst transmission. The data to be transmitted aretherefore combined into data packets. FIG. 1 shows the contents of onesuch data packet. It is formed by one LBR and one HBR part (LBR=low bitrate, HBR=high bit rate). The LBR part contains 35 bits with a length of680 ns each. The HBR part itself consists of a preamble of 450 bits (forreceiver synchronization and training and a selectable number m (0<m≦47)of data blocks with 496 bits each. The bit duration in the HBR part is42.4 nm (i.e. 1/16 of the bit duration in the LBR part).

The modulation format for the data in the LBR part is FSK (frequencyshift keying). The LBR part contains the destination address of thepacket. Based on this destination address the receiver can decidewhether it must process the following HBR part or not. The LBR part isnot detailed below, since it is not imperatively associated with theinvention.

FIG. 2 shows a block diagram of a coding and modulation process whichcorresponds to the ETS-HIPERLAN standard. Those parts which relate tothe processing of the LBR part have been omitted. Furthermore, it shouldbe noted that the block diagram represents only the so-called physicallayer. Above it is the MAC layer. The latter accepts the MPDU data(MPDU=MAC-Protocol Data Unit) in blocks of 416 bits. Each such block isdivided into 16 subblocks with 26 bits each. The subblocks are subjectedto a systematic (31, 26, 3) BCH code (BCH coder 1). This code has aHamming distance of 3. The resulting 16 BCH code words (with a length of31 bits each) are processed in interleaver 2. In doing so the code wordsare written into the columns of a matrix and are read out line by line.

In following toggling block 3 the bits are inverted in pairs (i.e., thebits with indices 2, 3, 6, 7, 10, 11 etc., the others are retainedunchanged). Toggling has no effect on the error behavior of the datatransmission process and is therefore not mentioned below.

Differential precoder 4 executes mod-2 addition of two successive bits:

    x(i)=Not (u(i) ⊕ u(i-1))

This is followed by mapper 5 which transforms the unipolar data intobipolar data for GMSK modulation (0→1, 1→-1). The described operationscan be shown more simply as follows

    x(i)=(u(i) ⊕ u(i-1))

    0→-1

    1→1

Finally, the symbols from mapper 5 are transferred to GMSK modulator 6for transmission at a frequency of for example 5.3 GHz.

GMSK is a frequency or phase increment modulation pattern in which phaseintegration is inherently contained. The HIPERLAN standard establishesthat bursts which are not completely error-free after demodulation andBCH decoding must be re-sent. Whether a received burst is regarded aserror-free or not after demodulation and BCH decoding is decided by thesubsequent decoding of a CRC code.

The differential precoding compensates this phase regulation andconverts the frequency (or phase increment) modulation pattern into aphase modulation pattern. For this reason the received signal ispredestined for demodulation with a coherent receiver. Decoding of thedata takes place then in principle by arranging the inverting blocks insuccession in reverse order (coherent demodulation, toggling,de-interleaving, BCH decoding, recovery of data from the code word).This is illustrated in FIG. 4.

The receiver-side processing described for coherent reception is howevernot feasible for noncoherent preceding. The integrator for cancellingthe differential preceding leads to unlimited error propagation. Asingle error in the noncoherent demodulator would lead to all successivebits being wrong. Subsequent BCH decoding then becomes useless. Systemperformance and especially the packet error rate become unacceptable.

As is apparent from FIG. 2, according to the invention in a receiverwith noncoherent demodulator 7, de-interleaver 8 and BCH decoder 9 areplaced in front of integrator 10. Element 11 is a code word to dataconverter. Element 11 is known in the art. ##EQU1## designates block n(0<n≦m) of a packet after coding and interleaving, this column of U(n)is then a code word. Due to interleaving, block U(n), as alreadymentioned, is read out line by line for subsequent precoding. ##EQU2##designates block n after differential precoding, it can be shown thatwith one exception each column X(n) is a BCH code word. Theaforementioned sole exception relates to first column x₁ (n). The latteris not necessarily a BCH code word. First bit x₁,1 (n) dependsspecifically on the last bit of the previous block:

    x.sub.1,1 (n)=x.sub.31, 16 (n-1) u.sub.1,1 (n)

The BCH coding used has a Hamming distance of 3. It was now possible toprove that the remaining 30 bits (x₂,1 (n) . . . x₃₁,1 (n)) form a codewith a minimum Hamming distance of 2. In this way it becomes possible toapply a soft-decision decoding process to the indicated 30 bits.

It should be watched that 15 of the total 16 columns of X(n) have stillremained BCH code words. Therefore BCH coding can be applied to thesecolumns in the conventional manner. This means that in 15 of the 16columns one individual error at a time can be corrected.

The first column can either be transferred directly to the output orprocessed with a soft decision decoding process. The soft decisiondecoding process ignores only the first bit of the first column. Allother bits are checked. The reliability information required for thesoft-decision decoding originates from the noncoherent demodulator.

One simple method of executing soft-decision decoding consists inignoring the bit encumbered with the greatest decision-makinguncertainty. Afterwards so-called erasure decoding can be used, i.e.,the most uncertain bit is reconstructed on the basis of existing coding.Based on the arrangement of the integrator according to the inventionthe packet error rate (relevant to HIPERLAN) does not suffer from theerror propagation effect.

The utility of soft-decision decoding depends largely on the feasiblecomputer cost (due to the decoder complexity) and the reliability of thesoft-decision decoding information.

FIG. 5 illustrates a method of a preferred embodiment. The flow chart ofFIG. 5 sets forth steps of the method disclosed.

In summary, it can be stated that the invention makes it possible tosimplify a HIPERLAN receiver in the demodulation stage. The inventioncan be used wherever on the transmitter side there are structurescomparable to the HIPERLAN standard and on the receiver side anoncoherent demodulator is desired.

We claim:
 1. A process for transmitting and receiving a signalcomprising the steps of:(a) first, BCH encoding the signal in accordancewith ETS-HIPERLAN standard, (b) second, differential pre-coding of theencoded signal in accordance with ETS-HIPERLAN standard, (c) modulatingthe pre-coded signal with a GMSK modulator, (d) demodulating themodulated signal with a non-coherent demodulator, (e) BCH decoding thedemodulated signal, and (f) integrating the decoded signal forcancelling transmitter-side differential pre-codingwherein saidintegrating step for cancelling transmitter-side differential pre-codingis executed only after BCH decoding.
 2. A process according to claim 1,wherein in BCH decoding the first code word of a data packet is excludedby error correction.
 3. A process according to claim 2, wherein thefirst code word is decoded with a soft-decision decoding process whichignores only the first bit of the code word.
 4. A process according toclaim 3, wherein the soft-decision decoding process operates accordingto an erasure decoding principle.
 5. A process according to claim 4,wherein the last bit of a preceding synchronization sequence is used forinitialization in integrating.
 6. A process according to claim 3,wherein the last bit of a preceding synchronization sequence is used forinitialization in integrating.
 7. A process according to claim 2,wherein the last bit of a preceding synchronization sequence is used forinitialization in integrating.
 8. A process according to claim 1,wherein the last bit of a preceding synchronization sequence is used forinitialization in integrating.
 9. A circuit comprising:means forreceiving a GMSK modulated signal, a non-coherent demodulator thatdemodulates the received GMSK modulated signal, a BCH decoder thatdecodes a signal derived from the demodulated signal, and an integrator,wherein the integrator follows BCH decoder as defined by signal flow forcancelling of differential precoding.